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atmel at88sa10hs atmel cryptoauthentication host security chip datasheet features ? secure key storage to complement the atmel ? at88sa100s and the atmel at88sa102 s devices ? superior sha - 256 hash algorithm ? guaranteed unique 48- bit serial number ? high speed si ngle wire interface, optionally shared with client ? supply voltage : 2. 7 ? 5. 2 5v ? 1.8 v ? 5.5 v communications voltage ? < 150 na sleep current ? 4kv esd protection ? multi - level hardware security ? secure personalization ? green compliant (exceeds rohs) 3 - pin sot - 23 and 8 - pin tssop or soic packages applications ? consumable device (battery, toner, other supplies) authentication ? network and computer access control ? authenticated communications for control networks ? anti - clone authentication for daughter cards ? physical access control (electronic lock and key) figure 1. pin configurations pin name function signal serial data , single - wire clock and data gnd ground vcc power supply nc nc nc gnd 1 2 3 4 8 7 6 5 8-lead soic vcc nc nc signal 3 2 1 gnd vcc signal 3-lead sot23 nc nc nc gnd 1 2 3 4 8 7 6 5 8-lead tssop vcc nc nc signal 8595g ? crypto ? 9 /11
atmel at88sa10hs [ datasheet ] 2 8595g ? crypto ? 9 /11 1. introduction the atmel cryptoauthentication ? family of chips is the first cost - eff ective authentication devices to implement the sha - 256 hash algorithm, which is part of the latest set of recommended algorithms by the us government. the 256- bit key space renders an y exhaustive attacks impossible. the at88sa10hs host version of cryptoau thentication chips is capable of validating the response coming from the sha -256 engine within an authentic cryptoauthentication client (sa100s or sa102s) , even if that response includes within the computation the serial number of the client. for detailed information on the cryptographic protocols, algorithm test values and usage models . see ? atmel at88sa100 s ? and ? atmel at88sa102 s? d atasheets, along with the application notes dedicated to this product family. the host cryptoauthentication performs three se parate operations (named host0, host1 , and host2) to implement this validation. the at88sa10hs chip takes both the challenge and response as inputs and returns a single boolean indicating whether or not the response is valid, in order to prevent the host c hip from being used to model a valid client. the host system is responsible for generating the random challenge that is sent to both the client and host cryptoauthentication devices as at88sa10hs does not include a random number generator. note: the chip implem ents a failsafe internal watchdog timer that forces it into a very low power mode after a certain time interval regardless of any current activity. system programming must take this into consideration. see section 5.5 for more details. 1.1 memory resources fuse block of 128- fuse bits that can be written through the one wire interface. fuse[87] ha s special meanings . see section 1.2 for more details. fuse s [88:95] are part of the manufactu rer id value fixed by atmel . fuse s [96:127] are part of the serial number programmed by atmel which is guaranteed to be unique. see section 1.3 for more details on the manufacturing id and serial number. rom metal mask program med memory. unrestricted reads are permitted on the first 64 - bits of this array. the physical rom will be larger and will contain other information that cannot be read. the following three fields are stored in the rom: rom mfr id 2 - bytes of rom that specif ies part of the manufacturing id code. this atmel assigned value is always the same for all chips of a particular model number. for the at88sa10hs, this value is 0x 2301 . (appears on the bus: 0x01 23) , rom mfrid can be read by accessing rom bytes 0 and 1 of a ddress 0 . rom sn 2 - bytes of rom that can be used to identify chips among others on the wafer. these bits reduce the number of fuses necessary to construct a unique serial number. the masksn is read by accessing rom bytes 2 and 3 of address 0 . the serial number can always be read by the system but is never included in the message digested by the host command. revnum 4 - bytes of rom that are used by atmel to identify the model mask and/or design revision of the at88sa10hs chip. these bytes can be freely rea d as the four bytes returned by rom a ddress 1; however , system code should not depend on this value as it may change from time to time.
atmel at88sa10hs [ datasheet ] 3 8595g ? crypto ? 9 /11 1.2 fuse map the at88sa10hs incorporates 128 one - time fuses within the chip. once burned, there is no way to reset the value of a fuse. all f uses, with the exception of the fuse mfrid and fuse sn bits initialized by atmel, have a value of one when ship ped from the atmel factory and transition to zero when they are burned. these fuses are burned at system personalization a nd cannot be changed after that time. table 1 -1. fuse map fuse # name description 0 ? 63 secret fuses these fuses can be securely written by the burnsecure command but can never be read with the read command 64 ? 86 status fuses these fuses can be written with the burnsecure command and can alway s be read with the read command 87 fuse dis able the host commands ignore the values of fuse[0 - 63] until this bit is burned . once this bit is burned, the burnsecure command is disabled 88 ? 95 fuse mfrid see section 1.3 . set by atmel, can no t be modified in the field 96 ? 127 fuse sn see section 1.3 . set by atmel, canno t be modified in the field secret fuses these 64 - fuses are used to augment the m ask programmed keys stored in the chip by atmel. knowledge of both the m ask keys and the values of the secret fuses are required to calculate the response value expected by host2. the burnsecure command can be used to burn an arbitrary sele ction of these 64 - bits. status fuses these 23 - fuses should be used to store information which is not secret, as their value can always be determined using the read command. typical usage would be model or configuration information. they cannot be automati cally included in the messages to be hashed by the host commands, but the system may read them and pass them back to host1 in the input stream if desired. fuse dis able this fuse is used to prevent access to fuses on chips in which a partial set of fuses ha s been burned. this fuse must be burned using the burnsecure command. 1.3 chip identification the chip includes a total of 72 - bits of information that can be used to distinguish between individual chips in a reliable manner. the information is distributed betw een the rom and fuse blocks in the following manner. serial number this 48 - bit value is composed of rom sn (16 - bits) and fuse sn (32- bits). together they form a serial number that is guaranteed to be unique for all devices ever manufactured within the cryp toauthentication family. this value is optionally included in the mac calculation. manufacturing id this 24 - bit value is composed of rom mfrid (16- bits) and fuse mfrid (8 - bits). typically this value is the same for all chips of a given type. it is always included in the cryptographic computations.
atmel at88sa10hs [ datasheet ] 4 8595g ? crypto ? 9 /11 1.4 key values the values stored in the at88sa10 h s internal key array are hardwired into the masking layers of the chip during wafer manufacture. all chips have the same keys stored internally, though the value o f a particular key cannot be determined externally from the chip. for this reason, customers should ensure they program a unique (and secret) number into the 64 - secret fuses and they should store the atmel provided key values securely. individual key value s are made available to qualified customers upon request to atmel and are always transmitted in a secure manner. when the serial number is included in the mac calculation , the response is considered to be diversified and the host needs to know the base sec ret in order to be able to verify the authenticity of the client. a diversified response can also be obtained by including the serial number in the computation of the value written to the secret fuses. the at88sa10hs provides a secure hardware mechanism to validate responses to determine if they are authentic. 1.5 sha - 256 computation at88sa10hs perform s only one cryptographic calculation ? a keyed digest of an input challenge. it optionally includes various other information stored on the chip within the digest ed message. the at88sa10hs computes the sha - 256 digest based on the algorithm documented here: http://csrc.nist.gov/publications/fips/fips180 - 2/fips180 - 2.pdf as a security measur e , the 24 - bit mfrid code (both rom and fuse bits) is automatically included in every message digested by at88sa10hs . the secret fuses are conditionally appended, depending on the parameters to the host command. for complete sample calculations, see ?a tmel at88sa100 s ? and/or ? atmel at88sa102 s? d atasheets. 1.6 security features at88sa10hs incorporates a number of physical security features designed to protect the keys from release. these include an active shield over the entire surface of the part, internal memor y encryption, internal clock generation, glitch protection, voltage tamper detection , and other physical design features. pre - programmed keys stored on at88sa10hs , are encrypted in such a way as to make retrieval of their values via outside analysis very d ifficult. both the clock and logic supply voltage are internally generated, preventing any direct attack via the pins on these two sign als. 2. io protocol communications to and from at88sa10hs ; take place over a single asynchronously timed wire using a pulse count scheme . the overall communications structure is a hierarchy: table 2 -1. io hierarchy tokens implement a single data bit transmitted o n the bus, or the wake - up event flags comprised of eight tokens (bits) which convey the direction and meaning of the next grou p of bits (if any) , which may be transmitted blocks d ata follow ing the command and t ransmit flags. they incorporate both a byte count and a checksum to ensure proper data transmission packets b ytes form ing the core of the block without the count and crc. they are either the input or output parameters of an at88sa10hs command or status information from at88sa10hs see applications n otes on the atmel website for more details on how to use any microprocessor to easily generate the signaling necessary to send these values to the chip.
atmel at88sa10hs [ datasheet ] 5 8595g ? crypto ? 9 /11 2.1 io tokens there are a number of io tokens input: (to at88sa10hs ) that may be transmitted along the bus: wake wake the at88sa10hs up from sleep (low power) state zero send a single bit from system to the at88sa10hs with a value of zero one send a single bit from system to the at88sa10hs with a value of one output: (from at88sa10hs ) zeroout send a single bit from the at88sa10hs to the system with a value of zero oneout send a single bit from the at88sa10hs to the system with a v alue of one the waveforms are the same in either direction, however there are some differences in timing based on the expectation that the host has a very accurate and consistent clock while at88sa10hs has significant variation in its internal clock genera tor due to normal manufacturing and environmental fluctuations. the bit timings are designed to permit a standard uart running at 230.4 k baud to transmit and receive the tokens efficiently. each byte transmitted or received by the uart corresponds to a si ngle bit received or transmitted by the at88sa10hs . see applications n otes on the atmel website for more details. 2.2 ac parameters t start t zhi t zlo data comm wake logic ? t start t bit logic 1 t lignore t hignore noise suppresion t wlo t whi
atmel at88sa10hs [ datasheet ] 6 8595g ? crypto ? 9 /11 3. absolute maximum ratings * operating temperature .................. ? 40 c to +85 c storage temperature ................. ? 65 c to + 150 c voltage on any p in with respect to ground ................ ? 0. 5 to v cc +0. 5 v *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condit ion beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. 4. ac parameters table 4 -1. ac parameters parameter symbol direction min typ max unit notes wake low duration t wlo to at88sa10hs 60 - s signal can be stable in either high or low levels during extended sleep intervals wake delay to data comm. t whi to at88sa10hs 2.5 45 ms signal should be stable high for this entire d uration. t whi must not exceed t timeout or the chip will transition to sleep start pulse duration t start to at88sa10hs 4.1 4.34 4.56 s from at88sa10hs 4.6 6.0 8.6 s zero transmission high pulse t zhi to at88sa10hs 4.1 4.34 4.56 s from at88sa 10hs 4.6 6.0 8.6 s zero transmission low pulse t zlo to at88sa10hs 4.1 4.34 4.56 s from at88sa10hs 4.6 6.0 8.6 s bit time ? t bit to at88sa10hs 37 39 - s if the bit time exceeds t timeout then at88sa10hs will enter sleep mode and the w ake token must be resent from at88sa10hs 41 54 78 s turn around delay t turnaround from at88sa10hs 28 60 95 s at88sa10hs will initiate the first low going transition after this time interval following the end of the transmit flag to at88sa10hs 15 s 45m s after at88sa10hs transmits the last bit of a block, system must wait this interval before sending the first bit of a flag high side glitch filter @ active t hignore_a to at88sa10hs 45 ns pulses shorter than this in width will be ignored by the chip, reg ardless of its state when active low side glitch filter @ active t lignore_a to at88sa10hs 45 ns pulses shorter than this in width will be ignored by the chip, regardless of its state when active low side glitch filter @ sleep t lignore_s to at88sa10hs 500 ns pulses shorter than this in width will be ignored by the chip when in sleep mode io timeout t timeout to at88sa10hs 45 65 85 ms see section 5.4.1 watchdog reset t wat chdog to at88sa10hs 3 4 5.7 s max. time from wake until chip is forced into sleep mode. see section 5.5 pause length t pause - 18 25 32 ms duration during which the chip will ignore io on the bus. see pauseshort command, section 6.7
atmel at88sa10hs [ datasheet ] 7 8595g ? crypto ? 9 /11 5. dc parameters table 5 -1. dc parameters parameter symb ol min typ max unit notes operating temperature t a - 40 85 c power supply voltage v cc 2.7 5.25 v fuse burning voltage v burn 3.0 5.25 v voltage applied to v cc pin . see s ection 6.6 active power supply current i cc - 6 ma sleep power supply current @ - 40 c to 55 c i sleep 150 na when chip is in sleep mode, v cc = 5.25v, vsig = 0.0 to 0.3v or vsig = v cc - 0.3 v to v cc sleep power supply current @ 85 c i sleep 1 a when chip is in sleep mode, v cc = 5.25v, vsig = 0.0 to 0.3 v or vsig = v cc - 0.3 v to v cc input low voltage @ v cc = 5.25 v v il - 0.5 0.75 v voltage levels fo r w ake token when chip is in sleep mode input low voltage @ v cc = 2.7 v v il - 0.5 0.5 v voltage levels for w ake token when chip is in sleep mode input high voltage @ v cc = 5.25 v v ih 1.5 5.25 v voltage levels for w ake token when chip is in sleep mode input high voltage @ v cc = 2.7 v v ih 1.25 3.0 v voltage levels for w ake token when chip is in sleep mode input low voltage when active v il - 0.5 0.5 v when chip is in active mode, v cc = 2.7 ? 5.25v input high voltage when active v ih 1.2 5.25 v when chip is in active mode, v cc = 2.7 ? 5.25v output low voltage v ol 0.4 v when chip is in active mode, v cc = 2.7 ? 5.25v maximum input voltage v max 5.25 v esd v esd 4 kv human body model, sig and v cc pins
atmel at88sa10hs [ datasheet ] 8 8595g ? crypto ? 9 /11 5.1 io flags the system is always the bu s master, so before any io transaction, the system must send an 8 - bit flag value to the chip to indicate the io operation that is to be performed, as follows: name meaning 0x66 command after this flag, the system starts sending a command block to the chi p. the first bit of the block can follow immediately after the last bit of the flag 0x99 transmit after a turn - around delay, the chip will start transmitting the response for a previ ously transmitted command block 0xcc sleep upon receipt of a sleep flag, the chip will enter a low power mode until the next w ake token is received all other values are reserved and will be ignored. note: t he values of flag for the at88sa10hs host are different from that of the two clients, the at88sa100 s and at88sa102 s . in this manner, both at88sa102 s (or at88sa100 s ) and at88sa10hs can share the same communications pin on the system controller. while the at88sa10hs will wake up when communications are sent to the client, it will ignore all such transactions. it is possible that data values transmitted to a client authentication chip (either the at88 ss100s or the at88sa102 s ) could be interpreted by the at88sa10hs host chip as a legal transmit flag. in this case there could be a bus conflict as both the host and client chips drive the signal wire at the same time. to prevent this, the pauseshort command should be used to prevent the at88sa10 hs host chip from looking at the signal wire during any io transaction to the client. 5.1.1 command timing after a command flag is transmitted, a com mand block should be sent to the chip. during parsing of the parameters and subsequent execution of a properly received command, the chip will be busy and not respond to transitions on the signal pin. the delays for these operations are listed in the table below: table 5 -2. command timing (guaranteed by design; not tested) parameter symbol max unit notes parsing delay t parse 100 s delay to check crc and parse opcode and parameters before an error indication will be available host 0 delay t exec_host0 1 3 ms delay to execute any of the host 0 command host 1 delay t exec_host1 7 ms delay to execute any of the host 1 command host 2 delay t exec_host2 0.5 ms delay to execute any of the host 2 command memorydelay t exec_read 3 ms delay to execute read command securedelay t ex ec_secure 3 6 ms max d elay to execute burnsecure command see section 6.6 for more details personalizedelay t person 1 3 ms delay to execute genpersonalizationkey in this document, t exec is used as shorthand for the delay corre sponding to whatever command has been sent to the chip.
atmel at88sa10hs [ datasheet ] 9 8595g ? crypto ? 9 /11 5.1.2 transm it flag the t ransmit flag is used to turn around the signal so that the at88sa10hs can send data back to the system, depending on its current state. the bytes that the at88sa10hs returns to th e system depend on its current state as follows: table 5 -3. return codes state description error/status description after w ake, but prior to first command 0x11 indication that a proper w ake token has been received by at88sa10hs after successful command execution ? return bytes per ?output parameters? in command section of this document. in some cases this is a single byte with a value of 0x00 indicating success. the t ransmit flag can be re - sent to at88sa10hs repeatedly if a re - read of the output is necessary execut ion error 0x0f command was properly receiv ed but could not be executed by at88sa10hs . changes in the at88sa10hs state or the value of the command bits must h appen before it is re - attempted after crc or other communications error 0xff command was not prope rly received by at88sa10hs and should be re - issued by the system. no attempt was made to execute the command the at88sa10hs always transmits complete blocks to the system, so in the above table , the status/error bytes result in four bytes going to the sy stem ? count, error, crc x 2. after receipt of a command block, the at88sa10hs will parse the command for errors, a process which takes t parse ( see section 5.1.1 ). after this interval the system can send a trans mit token to the at88sa10hs ? if there was an error , the at88sa10hs will respond with an error code. if there is no error , the at88sa10hs internally t ransitions automatically from t parse to t exec and will not respond to any transmit tokens until both delay s are complete. 5.1.3 sleep flag the sleep flag is used to transition the at88sa10hs to the low power state, which causes a complete reset of the internal command engine of the at88sa10hs and input/output buffer. it can be sent to at88sa10hs at any time when at8 8sa10hs will accept a flag. to achieve the specified i sleep , atmel recommends that the input signal be brought below v il when t he chip is asleep. to achieve i sleep if the sleep state of the input pin is high, the voltage on the input signal should be with in 0.3 v of v cc to avoid additional leakage on the input circuit of the chip. the system must calculate the total time required for all commands to be sent to the at88sa10hs during a single session, including any inter - bit/byte delays. if this total time ex ceeds t watchdog then the system must issue a partial set of commands, then a sleep flag, then a wake token, and finally after the w ake delay , issue the remaining commands.
atmel at88sa10hs [ datasheet ] 10 8595g ? crypto ? 9 /11 5.2 io blocks commands are sent to the chip, and responses received from the chi p, within a block byte n umber that is constructed in the following way : name meaning 0 count number of bytes to be transferred to the chip in the block, including count, packet and checksum, so this byte should always have a value of (n+1). the maximum s ize block is 39 and the minimum size block is four . values outside this range will cause unpredictable operation . 1 to (n -2) packet command, parameters and data, or response. see section 6 for more details. n - 1, n checksum crc- 16 verification of the count and packet bytes. the crc polynomial is 0x8005, the initial register value should be zero and after the last bit of the count and packet have been transmitted the internal crc register should have a value that matches that in the block. the first byte transmitted (n - 1) is the least significant byte of the crc value so the last byte of the block is the most significant byte of the crc. 5.3 io flow the general io flow for the commands is as follows: 1. system sends wake tok en 2. system sends transmit flag 3. receive 0x11 value from at88sa10hs to verify proper wakeup synchronization. 4. system sends command flag 5. syst em sends complete command block 6. system waits t parse for the at88sa10hs to che ck for command format ion errors 7. system sends transmit flag. if command format is ok, the at88sa10hs ignores this flag because the computation engine is busy. if there was an error, the at88sa10hs responds with an error code 8. system waits t exec , see section 5.1.1 9. system sends transmit flag 10. receive output block from the at88sa10hs , system checks crc 11. if crc from at88sa10hs is incorrect, indicating transmission erro r, system resends transmit flag 12. system se nds sleep flag to the at88sa10hs where the command in question has a short execution delay the system should omit steps six, seven and eight and replace this with a wait of duration t parse + t exec . 5.4 synchronization because the communications protocol is ha lf duplex, there is the possibility that the system and the at88sa10hs will fall out of synchronization with each other. in order to speed recovery, a t88sa10hs implements a timeout that forces the at88sa10hs to sleep. 5.4.1 io timeout after a leading transitio n for any data token has been received, at88sa10hs will expect the remaining bits of the token to be properly received by the chip within the t timeout interval. failure to send enough bits or the transmission of an illegal token (a low pulse exceeding t zlo ) will cause the chip to enter the sleep state after the t timeout interval. the same timeout applies during the transmission of the command block. after the transmission of a legal command flag, the io timeout circuitry is enabled until the last expected data bit is received. note that the timeout counter is reset after every legal token, so the total time to transmit the command may exceed the t timeout interval while the time between bits may not. in order to limit the active current if the at88sa10hs is inadvertently awakened, the io timeout circuitry is also enabled when the at88sa10hs receives a wake - up. if the first token does not come within the t timeout interval, the at88sa10hs will go back to the sleep mode without performing any operations. the io timeout circuitry is disabled when the chip is busy executing a command.
atmel at88sa10hs [ datasheet ] 11 8595g ? crypto ? 9 /11 5.4.2 synchronization procedures when the system and the at88sa10hs fall out of synchronization, the system will ultimately end up sending a t ransmit flag which will not generate a respons e from the at88sa10hs . the system should implement its own timeout which waits for t timeout during which time the at88sa10hs should go to sleep automatically. at this point, the system should send a wake token and after t wlo + t whi , a transmit token. the 0 x11 status indicates that the resynchronization was successful. it may be possible that the system does not get the 0x11 code from the at88sa10hs for one of the following reasons: 1. the system did not wait a full t timeout delay with the io signal idle in whi ch case the atmel at88sa10hs may have interpreted the w ake token and t ransmit flag as data bits. recommended resolution is to wait twice the t timeout delay and re - issue the wake token. 2. the at88sa10hs went into the sleep mode for some reason while the syste m was transmitting data. in this case, the at88sa10hs will interpret the next data bit as a w ake token, but ignore some of the subsequently transmitted bits during its wake - up delay. if any bytes are transmitted after the wake - up delay, they may be interpr eted as a legal flag, though the following bytes would not be interpreted as a legal command due to an incorrect count or the lack of a correct crc. recommended resolution is to wait the t timeout delay and re - issue the wake token. 3. there are some internal e rror condition s within the at88sa10hs which will b e automatically reset after a t watchdog interval, see below . there is no way to externally reset the at88sa10hs ? the system should leave the io pin idle for this interval and issue the wake token. 5.5 watchdog failsafe after the w ake token has been received by the at88sa10hs , a watchdog counter is s tarted within the chip. after t watchdog , the chip will enter sleep mode, regardless of whether it is in the middle of execution of a command and/or whether some io t ransmission is in progress. there is no way to reset the counter other than to put the chip to sleep and wake it up again. this is implemented as a fail - safe so that no matter what happens on either the system side or inside the various state machines of t he at88sa10hs including any io synchronization issue, power consumption will fall to the low sleep level automatically. 5.6 byte a nd bit ordering the at88sa10hs is a little - endian chip: ? all multi - byte aggregate elements within this spec are treated as arrays of bytes and are processed in the order received ? data is transferred to/from the at88sa10hs least s ignificant bit first on the bus ? in this document, the most significant bit and/or byte appears towards the left hand side of the page
atmel at88sa10hs [ datasheet ] 12 8595g ? crypto ? 9 /11 6. commands the c ommand packet is broken down in the following way: byte name meaning 0 opcode the command code 1 param1 the first parameter ? always present 2 -3 param2 the second parameter ? always present 4 + data optional remaining input data if a command fails be cause the crc within the block is incorrect or there is some other communications error , then immediately after t parse the system will be able to retrieve an error response block containing a single byte packet. the value of that byte will be all ones . in this situation, the system should re - transmit the command block including the proceeding transmit flag ? providing there is sufficient time before the expiration of the watchdog timeout. if the opcode is invalid, one of the parameters is illegal, or the at 88sa10hs is in an illegal state for the execution of this command , then immediately after t parse the system will be able to retrieve an error response block containing a single byte packet. the value of that byte will be 0x0f. in this situation, the condit ion must be corrected before the (modified) command is sent back to the at88sa10hs . if a command is received successfully , the system will be able to retrieve the output block as described in the individual command descriptions below after the appropriate execution delay . in the individual command description tables following , the ? size ? column describes the number of bytes in the parameter documented in each particular row. the total size of the block for each of the commands is fixed, though that value i s different for each command. if the block size for a particular command is incorrect, the chip will not attempt the command execution and return s an error.
atmel at88sa10hs [ datasheet ] 13 8595g ? crypto ? 9 /11 6.1 host0 concatenates the key stored in at88sa10hs with an input 256 - bit challenge and generates the digest of this message. the result is left in internal memory and cannot be read. in general, the challenge should be a random number generated by the host system, which will be sent to both the host ( at88sa10 hs ) and client ( at88sa100 s or at 88sa102 s). table 6 -1. input parameters name size notes opcode host0 1 0x08 param1 overwrite 1 if non - zero, overwrite part of internally generated key with secret fuses param2 keyid 2 the internal key to be used to generate the digest data challenge 32 challenge to be sent to the client at88sa100s or at88sa102s table 6 -2. output parameters name size notes success 1 upon successful completion of host0 , a value of zero will be returned by at88sa10hs the 512 - bit message block that will be hashed with the sha - 256 algorithm w ill consist of : 256- bits key[keyid] 256- bits challenge if the overwrite parameter is 0, then the 512- bit message block that will be hashed using the sha - 256 algorithm will consist of : 256- bits key[keyid] 2 56- bits challenge if the overwrite parame ter has a value of 0x01, then the 512 - bit message block that will be hashed using the sha - 256 algorithm will consist of : 192- bits key[keyid] 64- bits fuse[0 -63] 256- bits challenge all other values of the overwrite parameter are not recommended for us e.
atmel at88sa10hs [ datasheet ] 14 8595g ? crypto ? 9 /11 6.2 host1 completes the two block sha - 256 digest started by host0 and leaves the resulting digest within the internal memory of the at88sa10hs . this command returns an error if host0 has not been successfully run previously within this w ake cycle. as a security precaution, t his command does not return the digest . a subsequent command is required to compare the response generated by the client with the one generated by the host . table 6 -3. input parameters name size notes opcode host1 1 0x40 param1 mode 1 c ontrols composition of message, see below for details param2 zero 2 must be 0x00 00 data otherinfo 13 input po rtion of message to be digested table 6 -4. output parameters name size notes success 1 upon successful completion of host1 , a value of zero will be retur ned by at88sa10hs the contents of the second block to be digested are listed below. note: t o simplify this documentation; the bit addresses for otherinf o are listed in the table below size source notes 32- bits otherinfo[0 -31] opcode, param1 and param 2 valu es sent to at88sa100 s/ at88sa102 s 64- bits fuse[0 -63] if enabled by bit five of the input mode parameter and if fuse[87] is burned, else forced to zero 24- bits otherinfo[32 - 55] status fuse values from atsa100s/ at88sa102 s , or zeros 8 - bits fuse[88 - 95] fuse mfrid , should match between at88sa10hs and at88sa100 s/ at88sa102 s 32- bits otherinfo[56 - 87] fuse sn from at88sa100 s/ at88sa102 s (fuse[96 - 127]), or zeros 16- bits rom mfrid should match between at88sa10hs and at88sa100 s/ at88sa102 s 16- bits otherinfo[88 - 103] r om sn from at88sa100 s/ at88sa102 s , or zeros these bits are followed by the necessary ?1? bit, ?0? padding and 64 - bit length as specified in the sha - 256 specification. 6.2.1.1 mode encoding bit five of the mode is used to indicate whether or not the secret fuse bi ts are to be included in the calculation. the remaining bits of the mode field are ignored by at88sa10hs and should be zero . table 6 -5. mode encoding bit[5] fuse block 0 no fuse values inserted 1 insert the values of fuse[0 - 63] in the message if fuse[87] has not b een burned, then the values of fuse[0 - 63] will be replaced by zeros in the above message generation step as a security measure.
atmel at88sa10hs [ datasheet ] 15 8595g ? crypto ? 9 /11 6.3 host2 compares the value previously generated by the at88sa10hs using host0 and host1 with that on the input stream coming from the client and returns status to indicate whether or not the two matched. this command returns an error if host1 has not been previously successfully run within this w ake cycle. if the two digests do not match, the at88sa10hs provides no information as to the source of the mismatch, which must be deduced from the inputs to the three hostx commands. on a match failure, the entire set of host0, host1 , and host2 commands must be re - executed ? host2 cannot be repeatedly executed. table 6 -6. input parameters name size not es opcode host2 1 0x80 param1 zero1 1 must be 0x00 param2 zero2 2 must be 0x00 00 data clientresponse 32 response from the client table 6 -7. output parameters name size notes success 1 if the input clientresponse matches the internally generated response, a valu e of zero will be returned by at88sa10hs after a t host delay. if the two digests do not match, a value of 0x0f will be returned after a t host delay
atmel at88sa10hs [ datasheet ] 16 8595g ? crypto ? 9 /11 6.4 read reads 4 - bytes from fuse or rom; r eturns an error if an attempt is made to read any fuses or rom locations which are illegal. table 6 -8. input parameters name size notes opcode read 1 0x02 param1 mode 1 fuse or rom param2 address 2 which 4 - bytes within array. only bits zero and one are used, all others must be zeros data ignored 0 table 6 -9. output par ameters name size notes contents 4 the contents o f the specified memory location table 6 -10. mode encoding name value notes rom 0x00 reads four bytes from the rom. bit one of the address parameter must be zero fuse 0x01 reads the value of 32 - fuses. bit one of th e address parameter must be one
atmel at88sa10hs [ datasheet ] 17 8595g ? crypto ? 9 /11 6.5 genpersonalizationkey loads a personalization key into internal memory and then use s that key along with an input seed to generate a decryption digest using sha - 256. neither the key nor the decryption dig est can be read from the chip. upon completion, an internal bit is set indicating that a secure personalization digest has been loaded and is ready to use by the burnsecure command. this bit is cleared (and the digest lost) when the watchdog timer expires or the power is cycled. this command will fail if fuse[ 87 ] has been burned. table 6 -11. input parameters name size notes opcode genpers 1 0x20 param1 zero 1 must be 0x00 param2 keyid 2 identification number of the personalization key to be loaded data seed 16 see d for digest generation. the least significant bit of the last byte is ignored by at88sa10hs table 6 -12. output parameters name size notes success 1 upon successful execution, a value of 0 will be returned by atmel at88sa10hs the sha - 256 message body used to creat e the resulting digest internally stored in the chi p consists of the following 512 - bits: 256- bits personalizekey[keyid] 64- bits fixed value of all ones 127- bits seed from input stream 1 - bits ?1? pad 64- bits length of message in bits, fixed at 447
atmel at88sa10hs [ datasheet ] 18 8595g ? crypto ? 9 /11 6.6 burnsecure burns any combination of the first 88 - fuse bits. verification that the proper secret fuse bits have been burned must occur using the mac command ? there is no way to read the values in the first 64 - fuses to verify their state. the 24 - status fuses can be verified with the read command. the fuses to be burned are specified by the 88 - bit input map parameter. if a bit in the map is set to a ?1?, then the corresponding fuse is burned. if a bit in the map parameter is zero , then the corres ponding fuse is left in its current state. the first bit sent to at88sa10 h s corresponds to fuse[0] and so on up to fuse[87]. note: s ince a ?1? bit in the map parameter results in a ?0? data value in the actual fuse array, the value in the map parameter should be the inverse of the desired secret or status value. see section 1.2 for more details to facilitate secure personalization of the at88sa10 h s, this map may be encrypted before being sent to the chip. if this mode is desired, t hen the decrypt parameter should be set to one in the input parameter list. the decryption (transport) key is computed by the genpersonalizationkey command, which must have been run immediately prior to the execution of burnsecure. in this case, prior to b urning any fuses, the input map param eter is xor?d with the first 88 - bits of that digest from the genpersonalizationkey command. the genpersonalizationkey and burnsecure commands must be run within a single w ake cycle prior to the expiration of the watchdo g timer. the power supply pin must meet the v burn specification during the entire burnsecure command in order to burn fuses reliably. if v cc is greater than or equal to 3.7 v , then the burntime parameter should be set to 0x00 and the internal burn time will be 250 s. if vcc is less than 3.7 v but greater than v burn then the burntime parameter should be set to 0xffff and th e internal burn time will be 262ms per fuse bit burned . the chip does not internally check the supply voltage level. the total burnsecure e xecution delay is directly proportional to the total number of fuses being burned. if v cc is less than 3.7 v , then the total burnsecure execution time may exceed the interval remaining before the expiration of the watchdog timer. in this case, the burnsecur e command should be run repeatedly, with each repetition burning only as many fuses as there is time available. the system software is responsible for counting the number of ?1? bits in the clear - text version of the map parameter sent to the chip ? no erro r is returned if the fuse burn count is too high. other than fuse[87] (see below), the fuses may be burned in any order. prior to execution of burnsecure, at88sa10 h s verifies that fuse[87] is un - burned. if it has been burned, then the burnsecure command wi ll return an error. fuse[87] must be burned during the last repetition of burnsecure as it cannot be individually burned with burnfuse . there are a series of very small intervals during t exec_secure when the fuse element is actually being burned. during this in terval, t he power supply must not be removed and the watchdog timer must not be allowed to expire, or the fuse may end up in a state where it reads as un - burned but cannot be burned. table 6 -13. input parameters name size notes opcode burnsecure 1 0x10 param1 decr ypt 1 if 1 , decrypt map data before usage. if 0 , the m ap is transmitted in plain text param2 burntime 2 must be 0x00 00 if v cc > =3.7 v; must be 0xff ff otherwise data map 11 which fuses to burn, may be encrypted table 6 -14. output parameters name size notes success 1 upon successful execution, a value of zero will be returned by at88sa10hs this command takes a constant time to execute regardless of the number of fuses being burned.
atmel at88sa10hs [ datasheet ] 19 8595g ? crypto ? 9 /11 6.7 pauseshort forces the chip int o a busy mode for a period of t pause . during executi on of this command the chip will ignore all activity on the io signal. this command is used to prevent bus conflicts in a system that also includes one or more at88sa100 s or at88sa102 s client chips sharing the same signal wire. table 6 -15. input parameters name size notes opcode pauseshort 1 0x00 param1 ignored 1 must be 0x00 param2 ignored 2 must be 0x00 00 data ignored 0 table 6 -16. output parameters name size notes success 1 after a delay of t pause , the at88sa10hs will return a value of zero in response to a t ransmit fl ag
atmel at88sa10hs [ datasheet ] 20 8595g ? crypto ? 9 /11 7. pinout table 7 -1. pin definition s soic/tssop pin # name description 5 1 signal io channel to the system, open drain output. it is expected that an external pull - up resistor will be provided to pull this signal up to v cc for proper commu nications. when the chip is not in use this pin can be pulled to either v cc or gnd 8 2 v cc power supply, 2. 7 ? 5. 2 5 v . this pin should be bypassed with a high quality 0.1 f capacitor close to this pin with a short trace to gnd . see a pplications n otes on th e atmel website for more details 4 3 gnd connect to system ground 1,2,3,6,7 -- nc not connected
atmel at88sa10hs [ datasheet ] 21 8595g ? crypto ? 9 /11 8. p ackage drawing 3ts1 ? shrink sot p a c k a g e d r a w i n g c o n t a c t : p a c k a g e d r a w i n g s @ a t m e l . c o m t i t l e d r a w i n g n o . g p c r r e v . 3 t s 1 1 2 / 1 1 / 0 9 c o m m o n d i m e n s i o n s ( u n i t o f m e a s u r e = m m ) s y m b o l m i n n o m m a x n o t e e n d v i e w s i d e v i e w t o p v i e w 3 t s 1 , 3 - l e a d , 1 . 3 0 m m b o d y , p l a s t i c t h i n s h r i n k s m a l l o u t l i n e p a c k a g e ( s h r i n k s o t ) b t b g 0.89 0.01 0.88 2.80 2.10 1.20 0.30 a a1 a2 d e e1 l1 e1 b - - - 2.90 - 1.30 0.54 ref 1.90 bsc - 1.12 0.10 1.02 3.04 2.64 1.40 0.50 1,2 1,2 3 notes: 1. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusion s or gate burrs shall not exceed 0.25mm per end. dimension e1 does not include interlead flash or protrusion. interlead flash or protrusi on shall not exceed 0.25mm per side. 2. the package top may be smaller than the package bottom. dimensions d and e1 are determined at the outermost extrem es of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 3. these dimensions apply to the flat section of the lead between 0.08 mm and 0.15mm from the lead tip. this drawing is for general information only. refer to jed ec drawing to-236, variation ab for additional information. c l l1 3 e e1 1 2 e1 seat ing plan e b a2 a a1 e d gnd sd a v cc
atmel at88sa10hs [ datasheet ] 22 8595g ? crypto ? 9 /11 8 x ? t sso p package drawing contact: packagedrawings@atmel.com dr a wing n o . re v . title gpc common dimensions (unit of measure = mm) symbo l min nom max note a - - 1.20 a1 0.05 - 0.15 a2 0.80 1.00 1.05 d 2.90 3.00 3.10 2, 5 e 6.40 bsc e1 4.30 4.40 4.50 3, 5 b 0.19 ? 0.30 4 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 ref c 0.09 - 0.20 side v iew end v iew t op v iew a2 a l l1 d 1 e1 n b pin 1 indicator this corner e e notes: 1. this drawing is for general information onl y . refer to jedec drawing mo-153, v ariation aa, for proper dimensions, tolerances, datums, etc. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.15mm (0.006in) per side. 3. dimension e1 does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25mm (0.010in) per side. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. minimum space between protrusion and adjacent lead is 0.07mm. 5. dimension d and e1 to be determined at datum plane h. 8x d 6/22/11 8x, 8-lead 4.4mm bod y , plastic thin shrink small outline package (tssop) tnr c a1
atmel at88sa10hs [ datasheet ] 23 8595g ? crypto ? 9 /11 8s1 ? jedec soic package drawing contact: packagedrawings@atmel.com dra wing no . rev . title gpc common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.05 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 0 ? 8 ? e 1 n top view c e1 end view a b l a1 e d side view 8s1 g 6/22/11 notes: this drawing is for general information onl y . refer to jedec drawing ms-012, v ariation aa for proper dimensions, tolerances, datums, etc. 8s1, 8-lead (0.150? wide body), plastic gull wing small outline (jedec soic) swb
atmel at88sa10hs [ datasheet ] 24 8595g ? crypto ? 9 /11 9. ordering codes atmel at88sa10hs ordering information atmel ordering code package type vol tage range temperature range at88sa10hs - tsu - t so t, tape and reel 2.7 v? 5.25 v green compliant (exceeds rohs)/industrial (? 40c to 85c) at88sa10hs - t h - t tssop, tape and reel 2.7 v? 5.25 v green compliant (exceeds rohs)/industrial (? 40c to 85c) at88sa10hs - sh -t soic , tape and reel 2.7 v? 5.25 v green compliant (exceeds rohs)/industrial (? 40c to 85c) 10. revision history doc. rev. date comments 8595g 0 9 /2011 correct references and section numbers section 5.1.3 , sleep flag, change ? within 0.5 v of v cc ? to ?within 0.3v of v cc? 8595f 08/2010 update io timeout description 8595e 06/2010 update to tabl e 3: ac parameters 8595d 05/2010 expansion of io timeout specification 8595c 04/2010 added 8ld tssop 8595b 02/2010 updated parameter tables and added 8ld soic 8595a 04/2009 initial document release
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